Well it seems I went and made an instruction set. I don't currently plan on doing anything with it.
16-bit registers: R0, R1, R2, R3, R4, R5, R6, R7, and the program counter. R7 is also the stack pointer.
8-bit bank registers: BANK0, BANK1, BANK2, BANK3, BANKPC, BANKAB
There's also the status register with 4 condition code flags: zero, carry, signed overflow, and negative. Most instructions update the condition
code flags based on the result of the instruction. Conditional branches examine the flags.
Addresses are 24-bit. When using a register as a pointer, the register provides the lower 16 bits and a bank register provides the upper 8 bits.
By default, R0 and R1 use BANK0, R2 and R3 use BANK1, R4 and R5 use BANK2, R6 and R7 use BANK3, and the program counter uses BANKPC.
There could be a BANK register for each R register, but not doing that seems like an OK way to cut down on the number of registers.
Address modes:
--------------
Address modes are 6 bits within the instruction itself plus optional operands. rrr is the register number.
000rrr - register
001rrr - register pointer
010rrr - register pointer with post-increment
011rrr - register pointer with pre-decrement
100rrr - register pointer with displacement operand
101rrr - register pointer with bank operand
110rrr - register pointer with displacement and bank operands
111000 - 16-bit absolute address with upper 8 bits from BANKAB
111001 - 16-bit absolute address with upper 8 bits from BANKPC
111010 - 16-bit absolute address with bank operand
111011 - register pointer with index operand
111100 - register pointer with index and bank operands
111101 - program counter with displacement operand
111110 - program counter with displacement and index operands OR other register
111111 - immediate value (literal)
Displacement operand:
Signed 16-bit value
Address = register + displacement
Bank operand:
Determines the upper 8 address bits.
-----rrr bbbbbbbb
r - 0 to 3 = BANK#
4 = BANKPC
5 = BANKAB
6 = bbbbbbbb
This operand could be more compact if this thing were to have an 8-bit data bus.
Index operand for register pointer:
rrrRRRsd dddddddd
r - register 1
R - register 2
s - scale
0 - 1
1 - 2
d - displacement
Address = register 1 + register 2 * scale + displacement
Index operand for program counter
m--RRRsd dddddddd
m - mode
0 = remainder of operand is the same as index operand for register pointer, program counter is register 1
1 = RRR indicates register, s and d are ignored
0 to 3 = BANK#
4 = BANKPC
5 = BANKAB
6 = status register
Instructions:
-------------
s - source operand
d - destination operand
z - operation size (0 = 8-bit, 1 = 16-bit)
D - direction (0 = register is destination, address mode is source; 1 = register is source, address mode is destination)
r - register operand
a - address mode operand
i - immediate value
o - relative offset
c - condition
Instructions with a direction, register operand, and address mode operand do not allow D=1 and register address mode.
It would be redundant, and disallowing it saves the bit pattern for other instructions.
Size is indicated by a .B or .W suffix. For example, MOV.W R0, R1
Move
000zdddd ddssssss - MOV address, address
1101011r rriiiiii - MOV register, #0-63
Add
00100Dzr rraaaaaa - ADD register, address / ADD address, register
110111z0 00aaaaaa - ADD address, immediate (additional 16-bit operand)
111100zi iiaaaaaa - ADD address, #1-8
Subtract
00101Dzr rraaaaaa - SUB register, address / SUB address, register
110111z0 01aaaaaa - SUB address, immediate (additional 16-bit operand)
111101zi iiaaaaaa - SUB address, #1-8
Add with carry
00110Dzr rraaaaaa - ADC register, address / ADC address, register
110111z0 10aaaaaa - ADC address, immediate (additional 16-bit operand)
Subtract with carry
00111Dzr rraaaaaa - SBC register, address / SBC address, register
110111z0 11aaaaaa - SBC address, immediate (additional 16-bit operand)
And
01000Dzr rraaaaaa - AND register, address / AND address, register
110111z1 00aaaaaa - AND address, immediate (additional 16-bit operand)
Or
01001Dzr rraaaaaa - OR register, address / OR address, register
110111z1 01aaaaaa - OR address, immediate (additional 16-bit operand)
Xor
01010Dzr rraaaaaa - XOR register, address / XOR address, register
110111z1 10aaaaaa - XOR address, immediate (additional 16-bit operand)
Compare
01011Dzr rraaaaaa - CMP register, address / CMP address, register
110111z1 11aaaaaa - CMP address, immediate (additional 16-bit operand)
Test bit
01100Dzr rraaaaaa - TST register, address / TST address, register
1111100i iiaaaaaa - TST address, #0-7
Set bit
01101Dzr rraaaaaa - SET register, address / SET address, register
1111101i iiaaaaaa - SET address, #0-7
Reset bit
01110Dzr rraaaaaa - RES register, address / RES address, register
1111110i iiaaaaaa - RES address, #0-7
Toggle bit
01111Dzr rraaaaaa - TGL register, address / TGL address, register
1111111i iiaaaaaa - TGL address, #0-7
Arithmetic/logical shift left
10000Dzr rraaaaaa - ASL/LSL register, address / ASL/LSL address, register
100001zr rr000iii - ASL/LSL register, #1-8
Logical shift right
10001Dzr rraaaaaa - LSR register, address / LSR address, register
100011zr rr000iii - LSR register, #1-8
Arithmetic shift right
10010Dzr rraaaaaa - ASR register, address / ASR address, register
100101zr rr000iii - ASR register, #1-8
Roll left
10011Dzr rraaaaaa - ROL register, address / ROL address, register
100111zr rr000iii - ROL register, #1-8
Roll right
10100Dzr rraaaaaa - ROR register, address / ROR address, register
101001zr rr000iii - ROR register, #1-8
Roll left through carry
10101Dzr rraaaaaa - RLC register, address / RLC address, register
101011zr rr000iii - RLC register, #1-8
Roll right through carry
10110Dzr rraaaaaa - RRC register, address / RRC address, register
101101zr rr000iii - RRC register, #1-8
Multiply signed
10111D0r rraaaaaa - MULS register, address / MULS address, register
Multiply unsigned
10111D1r rraaaaaa - MULU register, address / MULU address, register
Divide signed
11000D0r rraaaaaa - DIVS register, address / DIVS address, register
Divide unsigned
11000D1r rraaaaaa - DIVU register, address / DIVU address, register
Short jump (8-bit signed offset, BANKPC unchanged)
1110cccc oooooooo - JMPS condition, absolute address
Jump (ignores bank, BANKPC unchanged)
110010cc ccaaaaaa - JMP condition, address
Long jump
110011cc ccaaaaaa - JMPL condition, address
Jump to subroutine (ignores bank, BANKPC unchanged, pushes 16-bit return address)
11001011 11aaaaaa - JRS address
Long jump to subroutine (pushes 24-bit return address)
11001111 11aaaaaa - JRSL address
Push effective address (ignores bank, pushes 16-bit address)
11010000 00aaaaaa - PEA address
Push long effective address (pushes 24-bit address)
11010010 00aaaaaa - PEAL address
Test (sets condition code flags)
110100z0 01aaaaaa - TST address
Clear
110100z0 10aaaaaa - CLR address
Not
110100z0 11aaaaaa - NOT address
Negate
110100z1 00aaaaaa - NEG address
Negate with carry
110100z1 01aaaaaa - NGC address
Swap halves
110100z1 10aaaaaa - SWAP address
Sign extend
110100z1 11aaaaaa - EXT address
Load effective address
1101010r rraaaaaa - LEA register, address
Exchange values
110110zr rraaaaaa - EXCH register, address / EXCH address, register
Return from subroutine (pops 16-bit return address)
00100010 00000000 - RTS
Long return from subroutine (pops 24-bit return address)
00100010 00000001 - RTSL
Return from interrupt
00100010 00000010 - RTI
No operation
00100010 00000011 - NOP
Halt
00100010 00000100 - HALT
Reset
00100010 00000101 - RESET
Copy R1 bytes from BANK0:R0 to BANK1:R2
00100010 00000110 - COPY
Decrement register, jump if register != 0 and condition is met
00101c1c cc000rrr - LOOP condition, register
Conditions:
-----------
0000 - Z/E (zero/equal)
0001 - NZ/NE (not zero/not equal)
0010 - P (positive)
0011 - N (negative)
0100 - CS/ULT (carry set/unsigned less than)
0101 - ULE (unsigned less than or equal)
0110 - CC/UGE (carry clear/unsigned greater than or equal)
0111 - UGT (unsigned greater than)
1000 - SLT (signed less than)
1001 - SLE (signed less than or equal)
1010 - SGE (signed greater than or equal)
1011 - SGT (signed greater than)
1100 - OS (overflow set)
1101 - OC (overflow clear)
1110 - no condition
320x224